Assessment of the difficulty in porting CPU architecture for arrayfire

[rax]

Hello everyone! I am working on implementing a tool to assess the complexity of CPU architecture porting. It primarily focuses on RISC-V architecture porting. In fact, it can be estimated on average across various architectures.My focus is on the overall workload and difficulty of transplantation in the past and future.As part of my dataset, I have collected the arrayfire project. I would like to gather community opinions to support my assessment. I appreciate your help and response! Based on scanning tools, the porting complexity is determined to be simple, with a small amount of code related to the CPU architecture in the project. (referring to the overall workload from adapting the project to a specific architecture to achieving full functionality on that architecture). Is this assessment accurate? I look forward to your help and response.

[syurkevi]

I think that assessment is accurate. Do double check your tool is only targeting the CPU backend. We use standard C++ code and porting the CPU backend shouldn't be too difficult. If you are targeting the OpenCL backend then you'd need a OpenCL 3.0 compliant runtime. Please let us know what other details you would need as we're not too familiar with RISC-V.