aritra1705

TReC

Calculate the similarity score among risc assembly files

OpenFPGA

An Open-source FPGA IP Generator

dotfiles

A collection of my personal dotfiles

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

asap7

Synthesis-Aware-Logic-Locking-Benchmarks

opentitan

OpenTitan: Open source silicon root of trust

aib-phy-hardware

Advanced Interface Bus (AIB) die-to-die hardware open source

gf180mcu-pdk

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

benchmarks

EPFL logic synthesis benchmarks

GNN-RE

GNN-RE datasets for circuit recognition

I99T

ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino

sky90fd-pdk

CEP-1

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

OMLA

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

prga

Open-source FPGA research and prototyping framework.

NetA

CEP

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

tiny_aes

AES

course-content-dl

NMA deep learning course

StdCellLib

LibreSilicon's Standard Cell Library

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

GNNUnlock

RANE

SAIL_GSC

FreePDK3

hw2vec