Anton Blanchard (antonblanchard)

antonblanchard

Geek Repo

Company:@tenstorrent

Twitter:@antonblanchard

Github PK Tool:Github PK Tool


Organizations
IBM

Anton Blanchard's repositories

microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

Language:VerilogLicense:NOASSERTIONStargazers:647Issues:41Issues:70

vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Language:PythonLicense:Apache-2.0Stargazers:102Issues:7Issues:16

chiselwatt

A tiny POWER Open ISA soft processor written in Chisel

Language:ScalaLicense:NOASSERTIONStargazers:101Issues:14Issues:5
Language:VerilogLicense:Apache-2.0Stargazers:5Issues:3Issues:0

qtrace-tools

Tools to read and write qtrace instruction traces

Language:CLicense:GPL-2.0Stargazers:5Issues:8Issues:1

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow

Language:VerilogLicense:BSD-3-ClauseStargazers:4Issues:2Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:2Issues:3Issues:1

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Language:VerilogLicense:Apache-2.0Stargazers:2Issues:2Issues:0

caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Language:VerilogLicense:Apache-2.0Stargazers:1Issues:2Issues:0

DFFRAM

Standard Cell Library based Memory Compiler using DFF cells

Language:VerilogLicense:Apache-2.0Stargazers:1Issues:2Issues:0

ghdl

VHDL 2008/93/87 simulator

Language:VHDLLicense:GPL-2.0Stargazers:1Issues:2Issues:0

linux

Linux kernel source tree

Language:CLicense:NOASSERTIONStargazers:1Issues:4Issues:0
Language:VerilogLicense:NOASSERTIONStargazers:1Issues:2Issues:0
License:Apache-2.0Stargazers:1Issues:0Issues:0

verilator

Verilator open-source SystemVerilog simulator and lint system

Language:C++License:LGPL-3.0Stargazers:1Issues:2Issues:0

ASAP7_for_KLayout

KLayout technology files for ASAP7 FinFET educational process

License:BSD-2-ClauseStargazers:0Issues:2Issues:0
License:Apache-2.0Stargazers:0Issues:0Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:0Issues:1Issues:0

lz4

Extremely Fast Compression algorithm

Language:CLicense:NOASSERTIONStargazers:0Issues:1Issues:0

lzo

Unofficial mirror of LZO

Language:CLicense:GPL-2.0Stargazers:0Issues:1Issues:0

magic

Magic VLSI Layout Tool

Language:CLicense:NOASSERTIONStargazers:0Issues:0Issues:0
Stargazers:0Issues:3Issues:0
Stargazers:0Issues:0Issues:0

netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists

Language:CLicense:NOASSERTIONStargazers:0Issues:2Issues:0

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.

Language:PythonLicense:Apache-2.0Stargazers:0Issues:2Issues:0

skywater-pdk-libs-sky130_fd_io

IO and periphery cells for SKY130 provided by SkyWater.

License:Apache-2.0Stargazers:0Issues:1Issues:0

smash

Smash - Compression Abstraction Library

License:MITStargazers:0Issues:0Issues:0

yosys

Yosys Open SYnthesis Suite

Language:C++License:ISCStargazers:0Issues:1Issues:0

zstd

Zstandard - Fast real-time compression algorithm

Language:CLicense:NOASSERTIONStargazers:0Issues:1Issues:0