Support Extended CPU Topology for AMD CPU/APU

[The Tumultuous Unicorn Of Darkness]

InstLatX64 spotted in AMD's Processor Programming Reference a Phoenix APU with "Performance Core" and "Efficiency Core" (source: https://twitter.com/InstLatX64/status/1639288284525342722).

I added the detection of these bits in 7542db9, but AMD statement about CPUID_Fn80000026_EBX register is clear:

CoreType. Read-only. Reset: Fixed,Xh. Defines per-core architectural feature differentiation (microarchitectural
resources, etc.) that may lead to a different performance, core clock boost, and power characteristic. Only valid
while LevelType=Core.

I think Extended CPU Topology leaf should be added to cpu_raw_data_t. Once done, a decode_amd_extended_topology() function could be added to get rid of workarounds in decode_amd_number_of_cores().

[Veselin Georgiev]

So this requires changing MAX_EXT_CPUID_LEVEL to at least 48 I guess (but we can make it 64 for a good measure).
A new lib version will be needed, since this breaks binary compatibility. But I think it's worth it.

Do you want to do it?

[The Tumultuous Unicorn Of Darkness]

There is no need to change MAX_EXT_CPUID_LEVEL if I am not mistaken. Extended CPU topology is CPUID_Fn80000026 (with sub-leaves).
However, a new member (uint32_t amd_fn80000026h[MAX_AMDFN80000026H_LEVEL][NUM_REGS]) is required in struct cpu_raw_data_t.
Yes, it will break binary compatibility so a new version will be required.

I can work on that (step-by-step, in a new branch). I will open a PR when I will start to work on that.