Jianfeng An's repositories
LogisimMIPS
Logisim MIPS examples.
VerilogMIPS-multicycle-uart
A multicycle MIPS processor for teaching.
Language:Scala000
ChiselMIPS
a MIPS example written by Chisel.
Language:Scala000
processor
For computer organization and computer architecuture lesson.
000
uart
A general UART design for FPGA debugging.
Language:Verilog000
VerilogMIPS-singlecycle
Verilog MIPS of Single cycle for teaching.
Language:Verilog000