Finish Wire/States

[Alexandre Moreno]

Error (10161): Verilog HDL error at Control.sv(139): object "ISNTR_DECODE" is not declared
Error (10161): Verilog HDL error at Control.sv(153): object "state" is not declared
Error (10161): Verilog HDL error at Control.sv(159): object "state" is not declared
Error (10161): Verilog HDL error at Control.sv(159): object "ADD" is not declared
Error (10161): Verilog HDL error at Control.sv(162): object "state" is not declared
Error (10161): Verilog HDL error at Control.sv(162): object "AND" is not declared
Error (10161): Verilog HDL error at Control.sv(165): object "state" is not declared
Error (10161): Verilog HDL error at Control.sv(165): object "SUB" is not declared
Error (10161): Verilog HDL error at Control.sv(168): object "state" is not declared
Error (10161): Verilog HDL error at Control.sv(168): object "XOR" is not declared
Error (10161): Verilog HDL error at Control.sv(171): object "state" is not declared
Error (10161): Verilog HDL error at Control.sv(171): object "BREAK" is not declared
Error (10161): Verilog HDL error at Control.sv(174): object "state" is not declared
Error (10161): Verilog HDL error at Control.sv(174): object "NOP" is not declared
Error (10161): Verilog HDL error at Control.sv(180): object "state" is not declared