amin1377 / StateMover

StateMover is a checkpoint-based debugging framework for FPGAs.

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StateMover

StateMover is a checkpoint-based debuggging framework for FPGAs. It allows the user to move the design state back and forth between an FPGA and a simulator. This enables a new style of debugging that combines the speed of hardware execution and the visibility and controllability of simulation.

Documentation

StateMover's documentation is available at Wiki

Papers

The following paper may be used as a general citation for StateMover:

S. Attia and V. Betz, "Stop and Look: A Novel Checkpointing and Debugging Flow for FPGAs," IEEE Transactions on Computers, 2021. Link

Bibtex:

@ARTICLE {StateMoverTC,
 author = {S. Attia and V. Betz},
 journal = {IEEE Transactions on Computers},
 title = {Stop and Look: A Novel Checkpointing and Debugging Flow for FPGAs},
 doi = {10.1109/TC.2021.3133828},
 year = {2022}
}

The following papers provide detailed info about StateMover tools:

S. Attia and V. Betz, "StateMover: Combining Simulation and Hardware Execution for Efficient FPGA Debugging," ACM FPGA, 2020. Link

S. Attia and V. Betz, "StateReveal: Enabling Checkpointing of FPGA Designs with Buried State," IEEE FPT, 2020. Link

S. Attia and V. Betz, "StateLink: FPGA System Debugging via Flexible Simulation/Hardware Integration," IEEE FPT, 2021. Link

About

StateMover is a checkpoint-based debugging framework for FPGAs.

License:MIT License


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Language:C++ 65.4%Language:LLVM 14.2%Language:Ada 10.5%Language:VHDL 4.9%Language:Verilog 4.4%Language:Tcl 0.5%Language:Python 0.0%Language:Shell 0.0%Language:C 0.0%Language:Makefile 0.0%Language:SystemVerilog 0.0%Language:Pascal 0.0%