amaranth-lang / amaranth-yosys

WebAssembly-based Yosys distribution for Amaranth HDL

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yosys-src compiling error

Godtec opened this issue · comments

Hello All:

trying to compile amaranth-yosys, not sure if it's a yosys issue or this repo problem.
Looks like it dies on the wasm-ld linker.

Any advice would be great! Thanks
Build environment: Ubuntu 20.04 X86.
Error output, below

Makefile.conf] ENABLE_PROTOBUF := 0
[Makefile.conf] ENABLE_ZLIB := 0
[Makefile.conf] 
[Makefile.conf] CXXFLAGS += -flto
[Makefile.conf] LDFLAGS += -flto -Wl,--strip-all
mkdir -p kernel/
ccache clang -o kernel/register.o -c  -target wasm32-wasi --sysroot /home/mikek/Documents/Cyclone_5/DECA_Board/amaranth-yosys/wasi-sdk-11.0/share/wasi-sysroot  -std=c++11 -Os -flto -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -I//include -flto -DYOSYS_DISABLE_SPAWN kernel/register.cc
mkdir -p frontends/verilog/
ccache clang -o frontends/verilog/preproc_stub.o -c  -target wasm32-wasi --sysroot /home/mikek/Documents/Cyclone_5/DECA_Board/amaranth-yosys/wasi-sdk-11.0/share/wasi-sysroot  -std=c++11 -Os -flto -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -I//include -flto -DYOSYS_DISABLE_SPAWN frontends/verilog/preproc_stub.cc
mkdir -p passes/cmds/
ccache clang -o passes/cmds/design_stub.o -c  -target wasm32-wasi --sysroot /home/mikek/Documents/Cyclone_5/DECA_Board/amaranth-yosys/wasi-sdk-11.0/share/wasi-sysroot  -std=c++11 -Os -flto -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -I//include -flto -DYOSYS_DISABLE_SPAWN passes/cmds/design_stub.cc
clang++ -o yosys.wasm -target wasm32-wasi --sysroot /home/mikek/Documents/Cyclone_5/DECA_Board/amaranth-yosys/wasi-sdk-11.0/share/wasi-sysroot  -Wl,-z,stack-size=1048576 -flto -Wl,--strip-all -flto -Wl,--strip-all kernel/version_85067f3.cc kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/mem.o kernel/yosys.o libs/bigint/BigInteger.o libs/bigint/BigUnsigned.o libs/sha1/sha1.o frontends/ast/ast.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verilog/preproc_stub.o frontends/verilog/const2ast.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_memwr.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/opt/opt_expr.o passes/cmds/plugin.o passes/cmds/design_stub.o passes/cmds/select.o passes/cmds/delete.o passes/memory/memory_collect.o passes/techmap/attrmap.o passes/techmap/flatten.o backends/rtlil/rtlil_backend.o backends/cxxrtl/cxxrtl_backend.o backends/verilog/verilog_backend.o  -lstdc++ -lm
wasm-ld: error: backends/verilog/verilog_backend.o: undefined symbol: Yosys::FfData::FfData(Yosys::FfInitVals*, Yosys::RTLIL::Cell*)
clang-10: error: linker command failed with exit code 1 (use -v to see invocation)
make: *** [Makefile:700: yosys.wasm] Error 1
make: Leaving directory '/home/mikek/Documents/Cyclone_5/DECA_Board/amaranth-yosys/yosys-src'

I'm not able to reproduce the issue you're having. What is the git revision for this repository and the yosys-src submodule you are using? Also, please attach the complete log.

Closing the issue as it's been more than six months. Please comment if you are still experiencing the issue.