aia39 / Arithmetic-Logic-Unit-ALU-Design-and-Simulation-In-Verilog-and-Proteus

This is a repository for our EEE 304 course project. The name of the course is Digital Electronics Laboratory. We have explored the ALU section of modern CPU using the concept of elementary digital electronics. Here verilog HDL was coded using Quartus II 9.0 version software and 4 bit ALU hardware design was done using Proteus software.

Arithmetic-Logic-Unit-ALU-Design-and-Simulation-In-Verilog-and-Proteus

This is a repository for our EEE 304 course project. The name of the course is Digital Electronics Laboratory. We have explored the ALU section of modern CPU using the concept of elementary digital electronics. Here verilog HDL was coded using Quartus II 9.0 version software and 4 bit ALU hardware design was done using Proteus software. For more details you can see our report.

Getting Started (Verilog Part)

• You have to unzip the zip file in 'verilog code' file.
• Open 'ALU3.qpf' for code script.
• You can use 'ALU3.vwf' for wave for generation.

Getting Started (Proteus)

• Open 'ALU_final.pdsprj' then you can run the simulation. Here you will see the hardware implementation of 13 operations using elementary digital electronics.

Requirements

• Proteus 8.6
• Quartus II 9.0

For video demonstration you can go through the whole video and implement yours.