agra-uni-bremen's repositories

riscv-vp

RISC-V Virtual Prototype

Language:C++License:MITStargazers:138Issues:17Issues:22

crave

Constrained random stimuli generation for C++ and SystemC

Language:C++License:NOASSERTIONStargazers:47Issues:14Issues:11

microrv32

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

Language:ScalaLicense:MITStargazers:37Issues:13Issues:0

BinSym

Symbolic execution for RISC-V machine code based on the formal LibRISCV ISA model

Language:HaskellLicense:MITStargazers:31Issues:5Issues:0

symex-vp

A concolic testing engine for RISC-V embedded software with support for SystemC peripherals

Language:C++License:GPL-3.0Stargazers:18Issues:12Issues:0

virtual-breadboard

Virtual Breadboard / PCB simulation for Prototyping and Educational Purposes

Language:C++License:MITStargazers:5Issues:0Issues:0

libriscv

Extensible implementation of the RISC-V ISA based on FreeMonads

Language:HaskellLicense:MITStargazers:4Issues:8Issues:0

opt-vp

Virtual Prototype for identifying Application Specific Hardware Optimization candidates

Language:C++License:MITStargazers:3Issues:8Issues:0

sifive-hifive1

This Repo contains documentation to the HiFive1 Board along with some example programs.

Language:CStargazers:3Issues:7Issues:0

SymSysC

Symbolic Execution of SystemC TLM Peripherals

Language:C++Stargazers:3Issues:8Issues:0

opt-seq

An algorithm to merge RISC-V instruction sequences

Language:C++License:MITStargazers:2Issues:9Issues:0

clover

A library for concolic execution of RV32 instruction set simulators

Language:C++License:GPL-3.0Stargazers:1Issues:10Issues:0

formal-iss

Generate an ISS for riscv-vp from a formal LibRISCV ISA model

Language:HaskellLicense:MITStargazers:1Issues:0Issues:0

virtual-bus

Simple protocol to connect two memory mapped buses (e.g. for Hardware In The Loop)

Language:C++Stargazers:1Issues:0Issues:0

vp-integration-tests

Tests for peripherals and other utilities of the riscv-vp

Language:CLicense:NOASSERTIONStargazers:1Issues:9Issues:0

hardbound-vp

Virtual Prototype with symbolic execution support and HardBound path analyzer

Language:C++License:GPL-3.0Stargazers:0Issues:9Issues:0

guix-symex

A Guix channel for reproducible symbolic execution research

Language:SchemeLicense:GPL-3.0Stargazers:0Issues:2Issues:0

icee2022-magic-adder-lib

Artifacts of the paper: "Investigating Various Adder Architectures for Digital In-Memory Computing Using MAGIC-Based Memristor Design Style"

License:MITStargazers:0Issues:9Issues:0
License:MITStargazers:0Issues:9Issues:0

libriscv-vp

RISC-V Virtual Prototype with ISS generated from LibRISCV

Language:C++License:MITStargazers:0Issues:0Issues:0
License:MITStargazers:0Issues:0Issues:0

spike-libriscv

Spike RISC-V simulator but with a autogenerated LibRISCV backend

Language:CLicense:NOASSERTIONStargazers:0Issues:0Issues:0

sps

Scheme library to specify network protocol state machines

Language:SchemeLicense:MITStargazers:0Issues:9Issues:0

sps-vp

Fork of SymEx-VP for specification-based symbolic execution of stateful network protocol implementations via SPS protocol specifications

Language:C++License:GPL-3.0Stargazers:0Issues:9Issues:0

symsysc-experiments

Experiments and DUTs for SymSysC repo

Language:C++Stargazers:0Issues:9Issues:0

systemc

SystemC Reference Implementation

Language:C++License:Apache-2.0Stargazers:0Issues:1Issues:0
License:MITStargazers:0Issues:0Issues:0

virtual-breadboard-protocol

Protocol definitions for SoC Environment simultations.

Language:C++Stargazers:0Issues:7Issues:0
Stargazers:0Issues:0Issues:0