Adwait Godbole's repositories
asplos24-micro-update-lifting
Companion artifact for ASPLOS '24: Lifting Micro-Update Models from RTL
-TAGE-based-Predictor-Verilog-Code
Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
adwait.github.io
Build a Jekyll blog in minutes, without touching the command line.
axiomatic-operational-examples
Experimental examples for axiomatic-operational
daikon
Dynamic detection of likely invariants
DB-Project
Parallel join optimisation scheme for PostgreSQL
llvmlite-dataflow
Generate dataflow graphs with the llvmlite Python library
multi_vscale
Verilog version of Z-scale (deprecated)
c3-simulator
C3-Simulator is a Simics-based functional simulator for the X86 C3 processor, including library and kernel support for pointer and data encryption, stack unwinding support for C++ exception handling, debugger enabling, and scripting for running tests.
Deterministic_Model
Deterministic_Models
helloworld
Getting Started
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
pyeda
Python EDA
pyvcd
Python package for writing Value Change Dump (VCD) files.
Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
riscv-sodor
educational microarchitectures for risc-v isa
sdram-controller
Verilog SDRAM memory controller
uclid
UCLID5: formal modeling, verification, and synthesis of computational systems
zipcpu
A small, light weight, RISC CPU soft core
zsim
A fast and scalable x86-64 multicore simulator