m0_rvalid is not 0 at reset?
whensungoesdown opened this issue · comments
masters' rvalid signal is not reset to 0. It is x until the first transaction finished.
sorry, i didn't think it through
AMBA bus generator including AXI4, AXI3, AHB, and APB
whensungoesdown opened this issue · comments
masters' rvalid signal is not reset to 0. It is x until the first transaction finished.
sorry, i didn't think it through