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adam-maj / tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

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Synthesis Using Quartus Prime

waleedjalilfarooqui opened this issue · comments

commented

How can I synthesize this using Quartus Prime ( windows). I have tried Adding the project and Running the files , but all i get are analysis error
Note : files are added as it is in project.
for Example :
Error (10170): Verilog HDL syntax error at scheduler.sv(18) near text: ")"; expecting an identifier. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10112): Ignored design unit "scheduler" at scheduler.sv(16) due to previous errors
Error (10644): Verilog HDL error at gpu.sv(170): this block requires a name
Error (10170): Verilog HDL syntax error at gpu.sv(193) near text: ")"; expecting ".", or an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10112): Ignored design unit "gpu" at gpu.sv(10) due to previous errors
Error (10170): Verilog HDL syntax error at fetcher.sv(27) near text: ")"; expecting a direction. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10112): Ignored design unit "fetcher" at fetcher.sv(7) due to previous errors

commented

I think the synthesiser didn't like the extraneous comma while passing in the parameter to the scheduler module

module scheduler #(
    parameter THREADS_PER_BLOCK = 4,
)

Removing it should fix the error I feel