aappleby / metron

A C++ to Verilog translation tool with some basic guarantees that your code will work.

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Options for nested structures

jcelerier opened this issue · comments

Hello, very interesting project.

My code uses a lot of

struct Foo {
  int x;
  struct Bar {
    int y;
  };
};

or

struct Foo {
  int x;
  struct {
    int y;
  } bar;
};

for grouping structures in DSP objects, a bit like this (as this enables relatively easy compile-time introspection and listing of field members in plain C++):

https://github.com/celtera/avendish/blob/main/examples/Raw/PerSampleProcessor.hpp

or this:

https://github.com/celtera/avendish/blob/main/examples/Raw/Random.hpp

I'm wondering if there is any deep thing that would prevent exposing the same thing to Metron, simply by prefixing names with the C++ names maybe ?