High % of CRC errors using T3S3
Tom-E opened this issue · comments
Hi,
Running at for example 500khz + SF12, I have ~20% CRC errors! From what I can tell, a TCXO should be able to help with this which I believe this board has? Do the examples use this correctly, if so why is the CRC % so high?
This is with an T3S3 v1.2 SX1262
Note that if I change to different settings, for example 62khz + SF5, the CRC error rate will drop to ~1%.
How can I reduce the % of CRC errors while keeping a longer range configuration?
DS_SX1261-2_V2_1.pdf
In the latest specification book released by semtech company, page 105
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