Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples

Home Page:http://xilinx.github.io/Vitis_Accel_Examples/

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Problem with accessing SSD from FPGA

omidrostamabadi opened this issue · comments

Hello,

I have an U.2 SmartSSD CSD (userguide).

Is there a way to access the SSD (read/write) from the FPGA kernel? I am aware of P2P buffers, but as far as I know, in order to copy data from SSD to P2P buffer in FPGA DDR memory, host needs to initiate the transfer. But in my use case, I need to communicate with SSD from the FPGA kernel, without any involvement of the host CPU.

Any help would be appreciated.

The examples under /host/p2p_simple, /host/p2p_bandwidthand /host/p2p_overlap_bandwidth utilize the P2P connection between the FPGA and SSD and the source code includes the required API. The tests also need to run with root access