Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples

Home Page:http://xilinx.github.io/Vitis_Accel_Examples/

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Vitis_Accel_Examples/hello_world example question

crizy opened this issue · comments

commented

i run hello_world example, HLS generate vadd.cpp kernel , i find TARGET_ADDR moved 1g with USER_ADDR genarate vadd rtl ip
as follows,

    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN)

I want to know 1g(32'hffffffff) how this is set up in hls,thans

Closing as requested to file case at Xilinx Forum.