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VUnit is a unit testing framework for VHDL/SystemVerilog

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Is there a way to specify minimum cycles between stalls for AXI stream VC?

cjmeyer opened this issue · comments

Some AXI-stream data streams that I need to simulate are inherently bursty meaning it will send a burst of data (for example, between 5 and 10 cycles of data back-to-back), and then go idle for some time (for example, between 2 and 4 cycles). For the AXI-stream VC, I see there is a way to set the stall probability and the min and max cycles when stalling, but no way to set a minimum or maximum number of cycles between stalls.

There is no such feature. What you can do is create a more custom stall by (randomly) interleaving your push and pop with wait_for_time(net, as_sync(master/slave), <some random time>)