No declaration within package instance

[ncervino]

Hello,

The code sample below causes VHDL-LS to generate a problem report with a message of No declaration of 'pkg1' within package instance 'pkg2'. The sample compiles without errors or warnings using ModelSim. Thanks for your help!

library ieee;
use ieee.std_logic_1164.all;

package pkg1 is
    generic(i_gen: natural);

    type type1_t is array (0 to i_gen) of std_logic_vector(i_gen - 1 downto 0);
end package pkg1;

package pkg2 is
    generic (i_gen : natural);

    package pkg1 is new work.pkg1 generic map (i_gen);

    type type2_t is array (0 to i_gen) of pkg1.type1_t;
end package pkg2;

entity ent is
end entity ent;

architecture arch of ent is
    package pkg2 is new work.pkg2 generic map (1);
begin
    process is
        variable v2 : pkg2.type2_t;
        variable v1 : pkg2.pkg1.type1_t;
    begin
        wait;
    end process;
end architecture arch;