Branch : Quicklogic : In symbiflow, AssertionError reported
rakeshm75 opened this issue · comments
In symbiflow, AssertionError reported:
make camif-ql-chandalar_jlink
Following error reported:
AssertionError: ('gpmc_ad(0)', 'FBIO_20')
make[3]: *** [quicklogic/tests/quicklogic_testsuite/camif/camif-ql-chandalar/ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp/top_iomux.jlink] Error 1
make[3]: *** Deleting file `quicklogic/tests/quicklogic_testsuite/camif/camif-ql-chandalar/ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp/top_iomux.jlink'
make[2]: *** [quicklogic/tests/quicklogic_testsuite/camif/CMakeFiles/camif-ql-chandalar_jlink.dir/all] Error 2
make[1]: *** [quicklogic/tests/quicklogic_testsuite/camif/CMakeFiles/camif-ql-chandalar_jlink.dir/rule] Error 2
make: *** [quicklogic/tests/quicklogic_testsuite/camif/CMakeFiles/camif-ql-chandalar_jlink.dir/rule] Error 2
rtl.zip
this is an assert in the jlink script generator. The bitstream itself is generated correctly. We'll take a look on the script
@rakeshm75 this is now fixed with antmicro/f4pga-arch-defs@c15f616
@kgugala , Thanks for providing this fix. While reviewing this script, we noticed that you are using the "mode" setting to set bit 5 and bit 11 on Pad config register. Actually for IOs used by FPGA, there is no need to set bit 5 and bit 11. They are only applicable when IO is not used by FPGA. In case of FPGA, OEN and REN are directly routed to FPGA interface. @rakeshm75 will send you a document to explain this. So you can skip setting these bits if ctrl_sel is Fabric.
This issue is resolved, so closing the issue.