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SpiNNaker peripheral interface

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SpiNNaker peripheral output support

lplana opened this issue · comments

commented

spif does not currently support SpiNNaker peripheral output.

Some of the hardware is already in place:

  • The SpiNNaker FPGAs do support peripheral output. The routing is done using peripheral routing key and mask registers.

  • spif demultiplexes SpiNNaker packets into configuration and peripheral streams. Configuration packets are handled by the spif register bank while peripheral packets are simply dumped.

Where should peripheral output be sent to?

The best option seems to be to send them over Ethernet to a peripheral device at a specified IP address/UDP port. There should be registers to hold these values. These registers should be accessible from SpiNNaker and should also be accessible from the peripheral. SpiNNaker should use the existing spif configuration route. Peripheral devices should send a UDP frame to spif directed at a known UDP port and spif will write the sender IP address and UDP port into these registers.

When should peripheral output be sent?

A UDP frame sholud be triggered when one of two conditions arises:

  1. the memory buffer holding events fills above a high watermark,
  2. a periodic timer triggers. The timer period should be configurable through a spif register. A default of 2ms seems adequate.

SpiNNaker packet to peripheral event mapping

It is not clear how spif should map SpiNNaker packet MC keys into peripheral events. Events may even need some form of data value that is carried as SpiNNaker packet payload. Simply reversing the input mapping does not appear to be a good solution.

spif output pipeline microarchitecture

  • spif HW should receive SpiNNaker packets, map them to peripheral events and store them in a memory buffer previously reserved for this purpose by the spif kernel module. The kernel module currently reserves memory for peripheral input only.

  • spif HW should interrupt spif SW when a UDP frame should be triggered, i.e., when one of the conditions listed above is met.

  • when interrupted, spif SW reads peripheral events from the memory buffer and sends them over Ethernet to the registered IP address and UDP port. It may need to send several UDP frames if the number of events exceeds the frame maximum size.

  • spif SW for peripheral output could be incorporated into spiffer as an additional thread.