sirv-e-sdk目录下的Makefile脚本如何输出elf和hex文件？

[xiaojia102003]

想跑一下仿真，不想用默认的verilog testcase。
但是看了一下Makefile脚本，并没有输出elf和hex的选项。
求助大神

[xiaojia102003]

or when i generate the hex file，how can i transfer the hex file to *.verilog or bin file----> the core can recognize format。。in generate dir？

[sopho]

riscv-none-embed-objcopy -O verilog *.hex *.verilog

riscv-tools/riscv-tests/isa/Makefile

[xiaojia102003]

riscv-none-embed-objcopy -O verilog *.hex *.verilog

riscv-tools/riscv-tests/isa/Makefile

Thank you , Got it. :）