SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

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DTM NOP overwrites a word in Debug RAM

brabect1 opened this issue · comments

Modules accessed through DTM are chip selected based only on DTM address field. In case of Debug RAM, the other control signal is RD (read/not write). RD maps to DTM Read operation, meaning that any other operation (e.g. NOP) will cause a write into DRAM.

wire dtm_req_sel_dbgram = (dtm_req_bits_addr[4:3] == 2'b0) & (~(dtm_req_bits_addr[2:0] == 3'b111));//0x00-0x06

The issue exploits the case for the Debug RAM, but other components may be affected too.

The fix is to condition DTM chip selects by DTM valid read or write operation.