Support for Bottom Boot Flash devices
dx4m opened this issue · comments
Hi, i wanted to ask if it is possible for you to add support for bottom boot flash chips?
I have a bunch of them here, that works normally when reading from it, but writing from the console is the big problem, because of the flipped sectors and the shifted address space.
Like a translation layer between the consoles normal top boot flash sectors and the bottom boot flash sectors. E.g. sector SA34(bottom) == SA0(top), sector SA33(bottom) == SA1(top), etc. And redirecting the addresses for read and write to the specific sectors. So that the CPLD behaves like with a Top Boot Device?
Page 14 and 15 from the Datasheet.
greez.
Hi,
The CPLD is at 100% capacity so translation layers like this are not possible at add.
Unfortunately you will need to use the correct flash chip.
Oh, that's a bummer. Never worked with CPLD's in the past, so the only way to implement such thing would be use of a FPGA instead of a CPLD?
Nevermind, I had them on hand so I thought it would be possible.
I've ordered the right ones now from Mouser with a heavy shipping cost. LCSC, where I order all my components, doesn't have them in stock.
The proper fix would be the modify XeniumOS to support different flash chips, unfortunately due to the source code never being released these types of changes are very difficult :(