Qucsator@Qucs: p-MOSFET placement influency convergence
ldpgh opened this issue · comments
Helllo, using the p-MOSFET (4-terminal device) of components/nonlinear_components its placement seems to influence the convergence if the Drain is connected to the power-supply rather than the Source.
Change(s) made to the parameters of p-MOSFET are
- Lambda=0.01
If the Source is connected to the power supply there are no convergence issues as far as I can tell.
Attached the testbench (inverter, input&output shorted). I_DIFF reports the difference of the current flowing through the inverters. The currents should be the same, if no other parameter is causing an asymmetrical behavior of the MOSFET.
n-MOSFET not checked for this issue.
Environment: Qucs 0.0.19 @ Win7Pro, i5-4310U
Screenshot
Qucs-Tesbench schematic ... filename extended by ".txt" to comply with Github
zt_pmosfet_orient.sch.txt
FYI ... simulation in LTspice creates warnings for all MOSFETs:
- Instance "m:inv1_1:t4": Length shorter than recommended for a level 1 MOSFET.
- Instance "m:inv1_1:t4": Width narrower than recommended for a level 1 MOSFET.
- ...
To prevent the warning in LTspice it seems the size should be >10um
Smells like a floating point comparison issue in LTspice regarding the geometry checker.
- 10e-06 still creates the warning
- 10.00000000000e-06 works fine
Geometry (W,L) = 10um
- Simulation runs smooth with a geometry of 10um (W,L)
- But DC-OP still fails if supply is set to 5V rather than ramping up in .TRAN
Default Geometry = 1um:
- it seems to speed up an inverter by factor 100x (just 20ps delay)
- very unrealistic behavior for Tox=100nm
Other comment ... origin of the issue was DC-OP failed:
- DC-OP is OK too, if the Source is connected to the power supply regardless the geometry.