PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

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# The task call part in veriloggen library is not generated correctly

Hikakkun opened this issue · comments

When you run the following, the task call part is not generated as expected

import veriloggen as vg

module = vg.Module("task_module")

clk = module.Input("CLK")
a = module.Input("a")
init_task = vg.Task("init")
init_task.Input("a")
init_task.Body()

module.add_task(init_task)
module.Always(vg.Posedge(clk))(
    init_task.call(a)
)

print(module.to_verilog())
module task_module
(
  input CLK,
  input a
);


  task init;
    input a;
    begin
    end
  endtask


  always @(posedge CLK) begin
    inita //init(a); is expected
  end


endmodule

my environment

  - python==3.12
  - pip==23.2.1
  - pip:
      - jinja2==3.1.2
      - markupsafe==2.1.3
      - numpy==1.26.2
      - ply==3.11
      - pyverilog==1.3.0
      - veriloggen==2.3.0