Help, how to make a verilog module from a Boolean expression

[Lucas Bragança]

Hi, I need to make a verilog module that calculates a boolean expression from an equation given as a string in python, Would you have an example of how to do this using veriloggen?
Ex:
python:
exp = A & B ^ ~C
Verilog:
module exp(input A, input B, input C, output exp);
assign exp = A & B ^ ~C;
endmodule

[Shinya T-Y]

See https://github.com/PyHDI/veriloggen/blob/master/tests/core/logic/logic.py.

from __future__ import absolute_import
from __future__ import print_function
import sys
import os

# the next line can be removed after installation
sys.path.insert(0, os.path.dirname(os.path.dirname(
    os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))

from veriloggen import *


def mkLed():
    m = Module('blinkled')
    a = m.Input('a')
    b = m.Input('b')
    c = m.Input('c')
    exp = m.Output('exp')

    exp.assign(a & b ^ ~c)

    return m

if __name__ == '__main__':
    led = mkLed()
    verilog = led.to_verilog()
    print(verilog)

[Shinya T-Y]

If a target expression (exp = a & b ^ ~c) is given as a text, it can be analyzed by using ast.parse() .

import ast
text = 'exp = a & b ^ ~c'
tree = ast.parse(text).body[0]
print(ast.dump(tree))

[Shinya T-Y]

Or, if a target expression is given as a python code, it should be analyzed by using inspect.getsource() in addition to ast.parser() .

import inspect
import textwrap
import ast

target = lambda a, b, c: a & b ^ ~c
text = textwrap.dedent(inspect.getsource(target))
tree = ast.parse(text).body[0]
print(ast.dump(tree))

[Shinya T-Y]

Anyway, please refer to the implementation of veriloggen.thread (embedded high-level synthesis) to get how to create Veriloggen objects from Python source codes.