Can this board boot without ram ?
Twisty59 opened this issue · comments
Hello,
I try to make this project for my A500, I did solder everything except the RAM & IDE parts but I get a black screen on DiagROM.
Can it boot without any ram chip or something is wrong with my soldering ?
Thanks you
Hello,
With DiagROM, RAM is not necessary and the Amiga should boot without issue. When using a real Kickstart ROM, you would enter a reset loop if the RAM is not fitted. A few points to check;
On the Amiga 68000 CPU connections, can you see (assuming CPLD is programmed and you have thoroughly checked your solder joints);
. /AS toggling?
./BERR or /HALT active?
.E CLK?
Hey,
Thanks you for your reply, yes the CPLD is programmed and verfied, this part should be good. I did reflow solder joints on the CPU and still get a black screen.
I'm really amateur in building a project like this, its is possible to check AS, BERR, CLK just with a multimeter or I will need an oscilloscope ?
Or maybe its possible to using a debug via jtag ? (I'm using an Raspberry Pi as JTAG interface)
Hello,
You really need a scope to check the behaviour of the signals changing state, however a Multimeter would work for some basic debugging.
You could use the Multimeter to determine if the /BERR and /HALT signals are active (active low so you should see a logic HIGH is they are not active). As for the /AS or E CLK, as they should be constantly changing the Multimeter might show a changing voltage or an average voltage. If it is stuck on logic LOW or HIGH then you know you have an issue.
You could send some pictures?
Thanks you for your help, I'll try to check that then.
Some pictures of my board
I've tested few point with multimeter
.E CLK have a constant 2.2v but I can't see the 30mhz signal with the multimeter
/HALT stay HIGH at 4,7v constant
/BERR stay HIGH at 5,1v constant
Looks like something is wrong..
Hello,
From the photos, some of the solder joints look a bit suspect. Have you checked for shorts between neighbouring pins on the CPLD and CPU? You can probe most of the signals on the 68000 DIP socket to make it simpler.
I did check every shorts between pins on the 68SEC000 but not the CPLD, i'll take a look tomorrow and maybe try to build a second board.
Hello,
I build my second board today and I've got the exact same problem, black screen on diagrom.
I did check solder joints with microspoe, check short on each pins and reflow everything but always same problem.
Hello,
Do you have serial output from DiagROM? Additionally, are you seeing the initial screen flashes? What XTAL frequency are you using? Can you use 10MHz or 16MHz as a test?
No screens flashes or power led blink, will try to see if serial say something.
I did try with a 30Mhz & 40Mhz, maybe thats too much.
Hello,
I'm currently working on an Amiga 600 version of the accelerator and I am finding the CPU isn't too happy over 30MHz. Try a lower frequency just to make sure the CPU isn't locking-up if the CLK is too high. I see you have the accelerator on a relocator board, if you replace the accelerator card with the plan CPU does it then work?
Heyy !
Few month later I made the board to boot just by replacing the Oscillator and its now booting on 30Mhz !
I still have some issue, only 1Mb on FastRAM is detected and I didn't manage to create a bootable adf for the IDE but I'm happy !
Hi there,
That is great news. The verilog actually only supports 1MEG. The hardware will support 2, however I never got around to updating it. When I get some time back I can try to make the updates- I actually have many “improvements” I would like to make.
Hi,
Thanks you so much for making this board real, it is very stable at 30Mhz, not a single crash.
Is it possible to get the correct ide.device for the IDE support ? Or maybe an .adf for booting because i'm a bit lost with this.
Thanks you :)
Hi There,
Check out the details here - [https://gitlab.com/MHeinrichs/AddBootNode] and also the AIDE reference project. You can create your own mountlist using the ide.deivce component. Additionally, HDToolBox could reference ide.device for the initial setup. As for a bootable ADF, there might be something on A1K.
Keep me updated how you go with this - in the meantime I will try and have a look for a link to the ADF on A1K.
Hello,
I have manage to get some sign of life of my IDE to CF Adaptater by using AddHD.
But something is wrong, AddHD Driveinfo show my CF with 80Go and its a 2Go.
Wich version of ide.device you was using for this board ?
Thanks for help :)
Hi There,
I created a ROM image with version 2.58 of ide.device using Remus. You can find version 2.59 here - [https://gitlab.com/MHeinrichs/AIDE/-/tree/master/device/new-version].
Hey,
I'll try to build one if it can autoboot with the ide.device and bootide.device but I have few questions.
Did you remove the scsi.device from previous rom ? base address for this board is $F20000 ?
Thanks :)
Hi There,
Yes, I had to remove scsi.device to make the other components fit. Base address of the IDE interface is 0xEF0000, which is the default for the ide.device.
Hello,
I have made my custom rom including ide.device and bootide.device and its still doesn't work.. my amiga boot and the HDD led stay light up but it doesn't boot on IDE.
I did try my rom with a simple AIDE board and its work great so I know my problem doesn't come from software part.
I have made your board twice and I do have this problem on both of them. So I have a few question :
I'm using 74HCT245D instead of 74HCT245, can it be the reason ?
Or maybe the CPLD firmware is not up to date on the github ?
I'm questioning about the firmware because both of my boards have a difference in terms of Dhrystones :
30Mhz Oscillator:
With a 36Mhz Oscillator:
At 36mhz i'm far away from you at 30mhz
Thanks you for your help 😄
Hi There,
I will try to summarise your questions with my feedback;
Q: I have made my custom rom including ide.device and bootide.device and its still doesn't work. What could it be?
A: When you boot via floppy, is the HDD visible within WB when connected to the accelerator? Using HDToolBox, you can try to change the DEVICE in the Icon ToolTypes to ide.device (from scsi.device) to check if the HDD is visible. Are you powering the HDD via PIN 20 on the IDE connector? On the current HW, PIN 20 is not routed to VCC.
Q: Could 74HCT245D be the reason?
A: No, I am using these parts as well.
Q: JED file version out of date?
A: I just rebuilt the JED and it is the same as the version in the repo.
Q: Why are the Dhrystones different?
A: In newer versions of the Verilog I inserted 2 WS into the RAM access to help with some other changes I was doing. Refer to line #402. I've created a JED without the WS for you to try (untested as I don't have my A500 setup at the moment).
P.S., if you are on Discord you can find me on "Official Commodore Amiga" or "Retro Tinkering".