DMAnext reads wrong byte value at low speed, but the `!DMA` (base/DMA) test didn't catch it b/c running at 28MHz

[Peter Ped Helcmanovsky]

Check if it's possible to expand the test meaningfully to test basic transactions also at low CPU speeds, verify with older Next cores if the issue is detected (the source must be outside of BRAM mirroring, ie. NOT in bank5/bank7).

exact conditions to replicate the bug should be:

• 2T/2T DMA timing, 3.5MHz CPU, mem->mem, non BRAM source mem.
• then instead of "0, 1, 2, 3" is read "?, 0, 1, 2"