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MisaghM / Computer-Architecture-Course-Projects

Verilog descriptions of MIPS single-cycle, multi-cycle & pipeline implementations.

Repository from Github https://github.comMisaghM/Computer-Architecture-Course-ProjectsRepository from Github https://github.comMisaghM/Computer-Architecture-Course-Projects

computer-architecturelinear-regressionmipsmips-architecturemips-assemblyverilog

Computer Architecture Course Projects

Projects for the computer architecture course at Tehran university.

MisaghM & PashaBarahimi

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Verilog descriptions of MIPS single-cycle, multi-cycle & pipeline implementations.

computer-architecturelinear-regressionmipsmips-architecturemips-assemblyverilog

License:MIT License

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Language:Verilog 54.8%Language:C++ 34.0%Language:Python 8.5%Language:Assembly 1.9%Language:Batchfile 0.8%