Please help with a makefile that puts src in its own dir

[Scott Hutter]

Hi, I am using your code as a base for mine, but the problem is that I cant seem to put .s and .c in a src folder. Id like to have:

project
---src
---obj
---target

Here's the makefile. It builds, but complains about not being able to find _start

`TOOL = arm-none-eabi
CFLAGS = -nostdlib -nodefaultlibs -nostartfiles -ffreestanding -fno-asynchronous-unwind-tables -fomit-frame-pointer -Wall -O3 -march=armv8-a -mfpu=neon-vfpv4 -mfloat-abi=hard -mtune=cortex-a53 -mno-unaligned-access -fno-tree-loop-vectorize -fno-tree-slp-vectorize -Wno-nonnull-compare -lc -lm -lgcc
LINKER_FLAGS = --no-wchar-size-warning --no-undefined -gc-sections --build-id=none -Bdynamic

BUILD_DIR = obj
SOURCE_DIR = src
TARGET_DIR = target

CSOURCE := $(wildcard $(SOURCE_DIR)/.c)
ASOURCE := $(wildcard $(SOURCE_DIR)/.s)

_COBJECT := $(patsubst %.c,%.o, $(CSOURCE))
_AOBJECT := $(patsubst %.s,%.o, $(ASOURCE))
AOBJECT = $(addprefix $(BUILD_DIR)/, $(notdir $(_AOBJECT)))
COBJECT = $(addprefix $(BUILD_DIR)/, $(notdir $(_COBJECT)))

all: kernel

Create the final binary

kernel: theelf
$(TOOL)-objcopy $(BUILD_DIR)/kernel.elf -O binary $(TARGET_DIR)/kernel8-32.img

Link all of the objects

theelf: $(AOBJECT) $(COBJECT)
$(TOOL)-ld $(LINKER_FLAGS) $(AOBJECT) $(COBJECT) -L. -Map $(BUILD_DIR)/kernel.map -T link32.ld -o $(BUILD_DIR)/kernel.elf

#build c files
$(BUILD_DIR)/%.o: $(SOURCE_DIR)/%.c
$(TOOL)-gcc -c $< -o $@ $(CFLAGS)

#build s files (Assembly)
$(BUILD_DIR)/%.o: $(SOURCE_DIR)/%.s
$(TOOL)-as $< -o $@

clean:
rm $(BUILD_DIR)/.o
rm $(BUILD_DIR)/.map
rm $(BUILD_DIR)/.elf
rm $(TARGET_DIR)/.img
`

[Leon de Boer]

Is this what you are trying to do it will just echo the filenames to screen

https://github.com/LdB-ECM/Exchange/blob/master/Makefile

[Scott Hutter]

Wow thank you. Makefiles are not my thing. Thats great.

…

On Tue, Aug 28, 2018 at 1:38 AM Leon de Boer ***@***.***> wrote: Is this what you are trying to do desired directory setup BUILD_DIR = obj SOURCE_DIR = src TARGET_DIR = target The names of all object files that must be generated. Deduced from the files in source directory. C_FILES := $(wildcard $(SOURCE_DIR)/*.c) Rule to is to make kernel.elf all: kernel.elf #this emuerates the c file list changing .c to .o and stripping filepath and adding in build_dir OBJDIR := $(BUILD_DIR) target = ${OBJDIR}/$(patsubst %.c,%.o,$(notdir ${1})) obj.c := define obj $(call target,${1}) : ${1} | obj$(suffix ${1}) += $(call target,${1}) endef define SOURCES $(foreach i,${1},$(eval $(call obj,${i}))) endef $(eval $(call SOURCES,${C_FILES})) #all those other c files will use this rule ${obj.c} : % : @echo <https://github.com/echo> other c file rule, $^ -o $@ rule says to build kernel.elf we need all those evaluated c objects kernel.elf : ${obj.c} @echo <https://github.com/echo> main file rule @echo <https://github.com/echo> $(C_FILES) Control silent mode .... we want silent in clean .silent:clean cleanup temp files clean: @echo <https://github.com/echo> the clean file rule — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#8 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AB0jiji3BE2vr94ds-XsM5vXuk5aPxN-ks5uVOVOgaJpZM4V_NTo> .