KylinChang / MulticycleCPU

The project aims to create a multi-cycle MIPS CPU based on FPGA board Nexy3.

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

This repository is not active

About

The project aims to create a multi-cycle MIPS CPU based on FPGA board Nexy3.


Languages

Language:VHDL 25.2%Language:HTML 22.0%Language:C 16.2%Language:Tcl 11.3%Language:Verilog 10.6%Language:Shell 7.6%Language:Stata 3.4%Language:Batchfile 3.3%Language:SystemVerilog 0.5%