Incorrect Bit Widths in Scan Chain with Multiple Faulty Regs

Question

Incorrect Bit Widths in Scan Chain with Multiple Faulty Regs

aroelke opened this issue 6 years ago · comments

If two Regs are annotated as being faulty with the same type of injector, they are reported in the scan chain to have the same width even if they don't in the Chisel code (it appears to be the minimum of the widths of the registers annotated). For example, if both reg_fflags and reg_frm in CSR.scala are annotated with StuckAt faults, scan-chain.json will report them to have widths of three even though fflags is five bits wide. This doesn't happen when the injectors are different.

I can't tell if this affects the final circuit, but it does affect the scan chain tool's ability to create a bitstream for LeChiffre.

Schuyler Eldridge · Answer 1 · Mon Jul 09 2018 20:17:44 GMT+0800 (China Standard Time)

This sounds like a bug to me. It may take me some time to get to this this week, but I'll add it to the unit tests. That should uncover whatever is going on.

aroelke · Answer 2 · Tue Jul 10 2018 04:24:12 GMT+0800 (China Standard Time)

I've started trying to fix this with PR #19, but I'm running into a problem with creating/loading the scan chain into LeChiffre. It works fine (i.e. passes my assembly test) if I only annotate one register as faulty, but if I annotate two or more the tests fail. How LeChiffre works and what it does to enable the injectors is hard for me to understand; do you know what might be going on?

aroelke · Answer 3 · Wed Jul 11 2018 02:23:02 GMT+0800 (China Standard Time)

I believe I figured it out. The transform was creating modules for each of the new injectors, but was only instantiating one of them (the rest were all instances of the first one). The latest update to PR #19 should address this.