Gurusatwik Bhatta N's repositories
PWM-Generator
This repository focuses on how to design a PWM Generator with variable Duty cycle
Language:VerilogMIT000
Verilog-HDL
Verilog-HDL
Language:VerilogMIT000
Gurusatwik
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The National Institute of Engineering, Mysuru
Mysuru
https://drive.google.com/file/d/1Nw0IXnLGOSMRc6w4PfW4iQjgfcS_86XY/view?usp=drive_link