[question] HDMI pixel clock limits

[Ilia Mirkin]

Various HDMI versions enable higher and higher pixel clocks. However individual GPUs are not required to support the maximum pixel clock supported by the spec in order to be compliant. It appears that some GPUs max out at 225MHz while others at 297MHz (while others still, I assume, are limited to 165MHz, esp among the older ones).

We've been unable to find this in the VBIOS (I had a thought that it was in the table pointed to by the 'T' table, but we have a counterexample to that). Could you suggest a way to find this information either from the VBIOS or based on the GPU? Are there differences between regular HDMI and DP -> HDMI (passive)?

This is becoming more and more relevant as 2560x1440/3840x2160 displays are become more common, while (dual-link) DVI-D is on its way out.

For now nouveau assumes Fermi = 225, Kepler+ = 297, but we definitely know that some Fermi's can do 297 (and the blob driver recognizes this fact).

[Andy Ritger]

Hi Ilia, sorry for failing to reply to this question for so long.

The logic for maximum pixelclock within the proprietary driver is convoluted, but for serial output resources (SORs) driving TMDS, I think it is effectively this:

if (SorIsDrivingHdmi) { 
    maxSingleLinkPixelClockKHz = SorCapMaxTMDSClkKHz; 
    maxPixelClockKHz = SorCapMaxTMDSClkKHz; 
} else { 
    if (SorCapDualTMDS) { 
        maxPixelClockKHz = 330000; 
    } else { 
        maxPixelClockKHz = 165000; 
    } 

    maxSingleLinkPixelClockKHz = 165000; 
} 

dongleLimit = ~0; 

if (passiveDpDongle == DP2DVI || passiveDpDongle == DP2HDMI_TYPE_1) { 
    dongleLimit = 165000; 
} 

if (passiveDpDongle == DP2HDMI_TYPE_2) { 
    dongleLimit = 300000; 
} 

maxPixelClockKHz = min(dongleLimit, maxPixelClockKHz); 
maxSingleLinkPixelClockKHz = min(dongleLimit, maxSingleLinkPixelClockKHz); 

(we use maxPixelClockKHz for mode validation, and maxSingleLinkPixelClockKHz to choose between single- and dual- link)

Where:

• passiveDpDongle is computed following the DP spec (I /think/, I didn't double check that this is defined in the DP spec, let me know if you need more on this).
• SorIsDrivingHdmi is TRUE if the EDID of the driven monitor contains a CEA861B EDID extension block.
• SorCapMaxTMDSClkKHz is computed by looking at EVO capability bits.
• SorCapDualTMDS is computed by looking at EVO capability bits.

SorCapDualTMDS and SorCapMaxTMDSClkKHz are computed like this:

if [gf100,gf119)
Read (0x006101E0+(sorIndex)*4)
SorCapDualTMDS = bit(11)
singleLinkTmds225 = bit(12)
SorCapMaxTMDSClkKHz = singleLinkTmds225 ? 225000 : 165000

if [gf119,...)
read (0x006301C4+(sorIndex)_2048)
SorCapDualTMDS = bit(11)
read (0x0063068C+(sorIndex)_2048)
SorCapMaxTMDSClkKHz = bits(23:16) * 10000;

Let me know if I can answer any other questions around that.

Sorry again for the slow response.

• Andy Ritger

[Ilia Mirkin]

Thanks for the detail. Based on what I'm reading, for pre-GF119, there's no way to ever have a single-link pixel clock > 225mhz, even if passiveDpDongle == DP2HDMI_TYPE_2 (I have no idea what these are btw, just reading the pseudocode). However we have at least one report of a GF106 user for whom the proprietary drivers support a 297MHz mode (and in practice it works fine too):

https://bugs.freedesktop.org/show_bug.cgi?id=91236

Am I misunderstanding your response, or is there more to it?

[Also, I'll have to double-check, but as I recall in the case of a passive dongle, there's no DPCD, and we don't do the usual DP link training/etc stuff, so we wouldn't even know it was a passive dongle there... details on how that's computed might be nice.]

[Andy Ritger]

I think the GF106 scenario would fall into the SorCapDualTMDS=true case, and result in maxPixelClockKHz = 330000.

I'll dig up how passiveDpDongle is computed.

[Ilia Mirkin]

You mean the !SorIsDrivingHdmi case? In that case, maxSingleLinkPixelClockKHz = 165000, and HDMI is never dual-link... or are you saying it'd be presented as dual-link anyways?

[Andy Ritger]

For the DP passive dongle detection: it looks like we do some i2c reads on the DDC bus to detect the dongle. I'm told this interoperability is dictated by the "VESA DisplayPort Dual-Mode Standard".

For the GF106 case: sorry, I didn't originally read the freedesktop.org bug, so I didn't realize this was HDMI. Reading the code, I must be missing something obvious, but from my read the proprietary driver's behavior in this case would match the pseudo code I described earlier, resulting in a 225MHz cap. I'll try to pull together a comparable hardware config and step through to see how this is getting validated with the proprietary driver.