STM32H743VGTx PLL clock validation error

[MStarha]

I am using this HAL v1.6.3 (currently latest) with STM32H743VGT6 MCU in a project of mine and I have found an error in the PLL clock validation code. In module crate::clocks::h in function validate_speeds() there are opposite inequality signs when checking VCO clocks.

This is the code that's there.

if let InputSrc::Pll1 = self.input_src {
    let pll_input_speed = self.pll_input_speed(self.pll_src, 1);
    if pll_input_speed < 1_000_000 || pll_input_speed > 16_000_000 {
        return Err(RccError::Speed);
    }
    // VCO0: Wide VCO range: 192 to 836 MHz (default after reset) (VCOH)
    // Note: The RM appears out of date: Revision "V" allgedly supports 960_000_000
    // VCO speed, to allow a max core speed of 480Mhz.
    let vco_speed = self.vco_output_freq(self.pll_src, 1);
    if pll_input_speed <= 2_000_000 && (vco_speed < 192_000_000 || vco_speed > 960_000_000)
    {
        return Err(RccError::Speed);
    }
    // 1: Medium VCO range: 150 to 420 MHz. (VCOL)
    // Note: You may get power savings
    if pll_input_speed > 2_000_000 && (vco_speed < 150_000_000 || vco_speed > 420_000_000) {
        return Err(RccError::Speed);
    }
}

but the lines should be like this:

...
if pll_input_speed > 2_000_000 && (vco_speed < 192_000_000 || vco_speed > 960_000_000)
...
if pll_input_speed <= 2_000_000 && (vco_speed < 150_000_000 || vco_speed > 420_000_000) {
...

This change matches Figure 47. PLL block diagram in RM0433 Rev 8, page 345/3353.

[David O'Connor]

Nice find; fixed.