0616ygh

PyTorchStepByStep

Official repository of my book: "Deep Learning with PyTorch Step-by-Step: A Beginner's Guide"

vicuna

RISC-V Zve32x Vector Coprocessor

RISC-V-Vector

Vector processor for RISC-V vector ISA

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

DREAMPlace

Deep learning toolkit-enabled VLSI placement

Limbo

Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

open_design_flow

OpenDesign Flow Database

OpenMPL

An open multiple patterning framework

FreePDK3

OpenCache

An open-source custom cache generator.

awesome-AI4EDA

This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for EDA.

Cyberrio

OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

rioschip_resubmission

svase

cheshire-ihp130-o

circt

Circuit IR Compilers and Tools

siliconcompiler

A modular build system for hardware

RISC-V-TensorCore

Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra

OpenABC

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

ML4Accel-Dataset

Dataset for ML-guided Accelerator Design

MLCAD-2023-FPGA-Macro-Placement-Contest

asap5

AutoGPT

AutoGPT is the vision of accessible AI for everyone, to use and to build on. Our mission is to provide the tools, so that you can focus on what matters.

OpenLANE-Sky130-Physical-Design-Workshop

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

betrusted-io.github.io

betrusted.io github page

bsg_sv2v

A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.